PicoNut Manual

Document History

Version	Date	Description
0.0.1	2024-04-03	Initial version (how to document, welcome page)

Introduction

Welcome to the PicoNut project! The PicoNut processor is a RISC-V processor being developed by the Efficient Embedded Systems Group (EESG) at the technical university of applied sciences Augsburg. The main goal of this project in its first phase is to provide a minimal RISC-V compatible architecture that is well documented and built to be expanded upon. Future prospects include the ability to run the Linux operating system and to support the RISC-V matrix extension to facilitate AI applications.

PicoNut Manual

• The PicoNut
• The PicoNut Project
  • System architecture
  • Software and Simulation
• The minimal Nucleus
  • Overview
  • Arithmetic Logic Unit (ALU)
  • Regfile
  • Program Counter (PC)
  • Instruction Register (IR)
  • Immediate Generator (immgen)
  • Byteselector
  • Extender
  • Datahandler
  • Controller
• IPort/DPort interface
  • Data Port (DPort)
  • Instruction Port
  • Data port and instruction port signals
  • Modes of operation
  • Timing diagrams
• UART
  • UART Registers
  • Wishbone UART
  • SimUART
• Software Library Documentation
  • Overview
  • Features
  • Getting Started
  • Library Components
  • c_soft_peripheral
  • c_soft_memory
  • c_soft_uart
  • Peripheral Interface
  • ELF Reader
  • Troubleshooting

Additional Resources

• How to Document
  • Introduction
  • Additional syntax provided by MyST
  • Tables
  • Images and Figures
  • Using draw.io diagrams
  • Doxygen
  • Tips and Workarounds
• Makesystem
  • Integrate a Core/Memu into the piconut toplevel
  • Adding a configuration option to the piconut
  • Creating a jenkins pipeline
• Block RAM Templates
  • Single Port Block RAM
  • Dual Port Block RAM
  • Dual Port Byte Enable Block RAM
  • Using a template in a design
• Appendix
  • Building the GNU Toolchain