The PicoNut Project

The PicoNut processor is an implementation of the RISC-V instruction set architecture (ISA) written in SystemC using the ICSC (Intel Compiler for SystemC) and YOSYS toolchains for FPGA deployment. The main motivation of the project as a whole is to provide an expandable and approachable platform for developers and users alike. For this purpose, the entire processor can be simulated using the powerful simulation capabilities of the SystemC C++ library. The modular nature of the PicoNut allows for an easy exchange of individual submodules for rapid prototyping.

With the initial release of this project the processor supports the RV32I subset of the RISC-V ISA and features a fully fledged simulation environment capable of running any C programs compiled using the standard gcc RISC-V toolchain. Future plans include implementing RISC-V extensions such as the A,F,M and V extensions with the aim of running the Linux operating system as well as enabling AI applications.

The following sections will give a short overview of the system architecture, hardware, software and simulation aspects of the project in its current iteration.

System architecture

The PicoNut processor itself is part of a larger system built around it. The processor core, the “memory unit” (MemU),a Wishbone bus and any kind of memory make up the required minimal system.

Memory is to be byte addressable and data is to be interpreted in LSB order by all components.

The Nucleus

The nucleus is the main component of the system. It is responsible for executing instructions, accessing memory and other devices via the memory unit in the process. Communication between the nucleus and the memory unit is done via the IPort/DPort interfaces.

Memory Unit

The memory unit serves as the processor nuclueus’ interface to the wishbone bus. It handles all read and write requests taken by the nucleus and forwards them to the wishbone bus. It does not equate to a memory management unit (MMU) at the time of release. Currently its primary function is address space separation to allow various peripherals connected to the wishbone bus to be addressed by the nucleus. Virtual memory, paging and cache functionality are future prospects.

Main system bus

The main system bus is an implementation of the Wishbone bus protocol. It connects the memory unit (which is connected to the Nucleus), the main memory and all peripherals.

Software and Simulation

To facilitate testing, debugging and rapid prototyping, the project includes a comprehensive simulator. It allows the user to provide the system with a gcc compiled program which is then run. Beyond allowing for standard output print statements, a .vcd trace file containing all processor core signal states, a core trace and a memory dump are generated alongside. To enable rapid integration of new peripherals in software only a simulation only software peripheral interface class is provided. The peripheral interface class “CSoftPeripheral” allows software models to interface with hardware models in simulation. This approach unlocks the speed, resources and features of the C++ language for the verification of hardware modules during the prototyping process, especially when potentially complex modules are required for the DUT to function.