Hardware Code Documentation
###########################

Description
===========

The hardwaremodules are currently written and tested in vhdl. 

Structure of the ``vhdl`` directory:

* ``vhdl/pkg`` : All custom vhdl libraries
* ``vhdl/src`` : All vhdl modules that are supposed to be deployed on the FPGA device
* ``vhdl/sim/modules`` : All vhdl modules that are integrated to run the simulation 
* ``vhdl/sim/testbenches`` : All vhdl modules that are simulation testbenches

.. note:
    When creating new modules it is required to copy or save the modules outside of the output directory next to the other 
    hardware description modules, since the output directory is not tracked via git and is cleaned up during builds. 

.. note:
    if new vhdl modules are integrated, please develop according to the established conventions in the "Conventions" chapter.

Package Modules
===============

.. note:
    The hardware files can be found in ``hw/vhdl/pkg``

.. vhdl:autopackage:: THANNA_TEST_UTILS
.. vhdl:autopackage:: THANNA_UTILS

THANNA_IP_CORE Modules
======================

THANNA_IP_CORE Modules
------------------------
.. note:
    The hardware files can be found in ``hw/vhdl/src``

.. vhdl:autoentity:: THANNA_IP_CORE
.. vhdl:autoentity:: AXI_MASTER
.. vhdl:autoentity:: MASTER_CONTROLLER
.. vhdl:autoentity:: AXI_SLAVE
.. vhdl:autoentity:: SLAVE_CONTROLLER    


Simulation Setup Modules 
------------------------
.. note:
    The hardware files can be found in ``hw/vhdl/sim/modules``

.. vhdl:autoentity:: MAIN_SIM 
.. vhdl:autoentity:: DDR_SIM     

AXI_TEST Engine Core Modules  
============================

.. note:
    The hardware files can be found in ``hw/vhdl/sim/testbenches``  

.. vhdl:autoentity:: AXI_TEST
.. vhdl:autoentity:: BURST_REG

AXI_TEST Simulation Modules
---------------------------

.. note:
    The hardware files can be found in ``hw/vhdl/sim/testbenches``  

.. vhdl:autoentity:: INTERFACE_TB

GENERAL MODULES
===============

.. note:
    These are modules that can be used in any core. 
    The hardware files can be found in ``hw/vhdl/src/general``

.. vhdl:autoentity:: COUNTER
.. vhdl:autoentity:: SINGLEPORT_BRAM
.. vhdl:autoentity:: DUALPORT_BRAM
.. vhdl:autoentity:: FIFO
.. vhdl:autoentity:: DSP_MAC
.. vhdl:autoentity:: RING_BUFFER

GENERAL SIMULATION MODULES
==========================

.. note:
    These are the unit tests for modules that can be used in any core. 
    The hardware files can be found in ``hw/vhdl/sim/testbenches/general``

.. vhdl:autoentity:: COUNTER_TB
.. vhdl:autoentity:: FIFO_TB
.. vhdl:autoentity:: RING_BUFFER_TB


SINGLE_ENGINE_CORE Modules 
==========================

.. note:
    These are the ``SINGLE_ENGINE_CORE`` including the tobmodule. 
    The hardware files can be found in ``hw/vhdl/src/SINGLE_ENGINE_CORE``

.. vhdl:autoentity:: BRAM_CACHE
.. vhdl:autoentity:: MAC_BLOCK
.. vhdl:autoentity:: MAC_PIPELINE
.. vhdl:autoentity:: READ_BUFFER
.. vhdl:autoentity:: REC_ADDER
.. vhdl:autoentity:: RELU
.. vhdl:autoentity:: RING_ACCUMULATOR
.. vhdl:autoentity:: SLIDING_WINDOW_BUFFER
.. vhdl:autoentity:: WINDOW 
.. vhdl:autoentity:: WRITE_BUFFER 


SINGLE_ENGINE_CORE Simulation Modules 
=====================================

.. note:
    These are the ``SINGLE_ENGINE_CORE`` testbenches. 
    The hardware files can be found in ``hw/vhdl/sim/testbenches/SINGLE_ENGINE_CORE``

.. vhdl:autoentity:: BRAM_CACHE_TB
.. vhdl:autoentity:: MAC_BLOCK_TB
.. vhdl:autoentity:: MAC_PIPELINE_TB
.. vhdl:autoentity:: READ_BUFFER_TB
.. vhdl:autoentity:: RELU_TB
.. vhdl:autoentity:: RING_ACCUMULATOR_TB
.. vhdl:autoentity:: SLIDING_WINDOW_BUFFER_TB
.. vhdl:autoentity:: WINDOW_TB
.. vhdl:autoentity:: WRITE_BUFFER_TB