Hardware

The documentation contains:

• 1. An Overview of the Hardware Repository
  • 1.1. Make System
  • 1.2. TCL
  • 1.3. The Output Directory
  • 1.4. Hardware Description
  • 1.5. Board Files
  • 1.6. Wavewindow Files
  • 1.7. Python Testbench Scripts
• 2. An Overview of the Hardware structure
  • 2.1. System Level
    • 2.1.1. Description
    • 2.1.2. Block Design
  • 2.2. IP Core Level
    • 2.2.1. Description
    • 2.2.2. Modules
    • 2.2.3. Interfaces
  • 2.3. The Engine Core Level
    • 2.3.1. Description
• 3. Current state of Implementation
  • 3.1. THANNA Core Framework
  • 3.2. SINGLE Engine Core
• 4. An How To File for interaction
  • 4.1. How to simulate
  • 4.2. How to generate hardware
• 5. All relevant Interfaces
  • 5.1. Hardware Interfaces
    • 5.1.1. SLAVE_CONTROLLER_INTERFACE
    • 5.1.2. MASTER_CONTROLLER_INTEFACE
  • 5.2. Software Interfaces
    • 5.2.1. SLAVE_CONTROLLER_INTERFACE
    • 5.2.2. AXI_TEST_ENGINE_CORE_INTERFACE
• 6. Code Conventions
  • 6.1. VHDL Naming and Syntax Conventions
  • 6.2. General Conventions
  • 6.3. Naming Conventions
  • 6.4. State Machine and Processes
• 7. Code Documentation
  • 7.1. Description
  • 7.2. Package Modules
  • 7.3. THANNA_IP_CORE Modules
    • 7.3.1. THANNA_IP_CORE Modules
    • 7.3.2. Simulation Setup Modules
  • 7.4. AXI_TEST Engine Core Modules
    • 7.4.1. AXI_TEST Simulation Modules
  • 7.5. GENERAL MODULES
  • 7.6. GENERAL SIMULATION MODULES
  • 7.7. SINGLE_ENGINE_CORE Modules
  • 7.8. SINGLE_ENGINE_CORE Simulation Modules
• 8. Simulation
  • 8.1. End-to-end setup
    • 8.1.1. Hardware
    • 8.1.2. Software
    • 8.1.3. How to simulate
  • 8.2. Unit Tests