4. How to

4.1. How to simulate

The following is an example of simulating an end-to-end test, using the interface test.

1. Generate the simulation project:

   • Navigate to the hardware directory: cd ./hw

   • Run: make sim_interface

   • The output mem.txt file will be available immediately for review at hw/out/sim_interface/sim_interface.sim/sim_1/behav/xsim/mem.txt.

2. For further signal analysis in Vivado:

   • Open the project in Vivado: vivado hw/out/sim_interface/sim_interface.xpr

   • To regenerate the text file, use: python sim/sim_interface.py --path out/sim_interface/sim_interface.sim/sim_1/behav/xsim/mem.txt

   • Optionally, load a corresponding wave configuration file into the waveform viewer in Vivado. For this test, use wavefile/INTERFACE_TB.wcfg.

   • Start the simulation and analyze the signals.

4.2. How to generate hardware

Generating hardware involves 2 steps

1. Check hardware files:

   • Look into the ./vivado.tcl file

   • Ensure all desired vhdl files are referenced in the src_files list

2. Run the make process:

   • Navigate to the hardware directory: cd ./hw

   • Run make thanna_ip_core to generate the ip_core

   • Run make system to generate the environment around the ip_core

   • Run make update_system to synthesize and implement all

   • Now in the ./out/system folder the vivado project can be opened

   or the xsa bitstream file taken to launch it via thannOs