3. Current State of Implementation

3.1. THANNA Core Framework

The THANNA_IP_CORE interface framework is fully working and also integrated with the AXI_TEST module in the master branch. It can be simulated and also runs on the hardware.

3.2. SINGLE Engine Core

The Single Engine Core is neither fully implement nor every testbench works. Furthermore a general testbench that tests a convolution or fc layer is missing.

Missing work:

  • Ring Accumulator is currently not tested

  • MAC_PIPELINE is not fully implemented. Reason of the reimplementation is to avoid recursive instantiation and ensure

that no further data is required to be inputed in order to compute all outputs

  • MAC_BLOCK is not tested with the new testbench

  • Simple register Module after the SLIDING_WINDOW_BUFFER is required, that simply holds the SWB output when a

a fully connected layer is computed

Steps after that:

  • Create a general simulation testbench similiar to INTERFACE_TB, but with instructions to perform convolutions and fc computations

  • Test the implementation in hardware