7. Hardware Code Documentation
7.1. Description
The hardwaremodules are currently written and tested in vhdl.
Structure of the vhdl directory:
vhdl/pkg: All custom vhdl librariesvhdl/src: All vhdl modules that are supposed to be deployed on the FPGA devicevhdl/sim/modules: All vhdl modules that are integrated to run the simulationvhdl/sim/testbenches: All vhdl modules that are simulation testbenches
7.2. Package Modules
- PACKAGE THANNA_TEST_UTILS IS
The package includes all sorts of test utilities: rand_slv: A function to generate a random slv run_cycle: Stimulate a clock cycle run_half_cycle: Stimulate half a clock cycle assert_sl: Compare two std_logic signals assert_slv: Compare two std_logic signals
- PACKAGE THANNA_UTILS IS
The package includes all sorts of test utilities: rand_slv: A function to generate a random slv run_cycle: Stimulate a clock cycle run_half_cycle: Stimulate half a clock cycle assert_sl: Compare two std_logic signals assert_slv: Compare two std_logic signals
7.3. THANNA_IP_CORE Modules
7.3.1. THANNA_IP_CORE Modules
- ENTITY THANNA_IP_CORE IS
THANNA_IP_CORE top module. It contains all the AXI logic and the engine core top modules.
Generics
PortsGeneric
Type
Default
Description
NUMBER_OF_CORES
natural
2
AXI_BURST_LEN
natural
16
parameters of axi slave bus interface s00_axi AXI_DATA_WIDTH : natural := 32; AXI_ADDR_BW : natural := 5; parameters of axi master bus interface m00_axi
AXI_ID_WIDTH
natural
1
AXI_ADDR_BW
natural
32
AXI_DATA_WIDTH
natural
32
AXI_AWUSER_WIDTH
natural
1
AXI_ARUSER_WIDTH
natural
1
AXI_WUSER_WIDTH
natural
1
AXI_RUSER_WIDTH
natural
1
AXI_BUSER_WIDTH
natural
1
Port
Type
Mode
Description
s00_axi_aclk
std_logic
in
ports of axi slave bus interface s00_axi
s00_axi_aresetn
std_logic
in
s00_axi_awaddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s00_axi_awprot
std_logic_vector(2 downto 0)
in
s00_axi_awvalid
std_logic
in
s00_axi_awready
std_logic
out
s00_axi_wdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
s00_axi_wstrb
std_logic_vector((AXI_DATA_WIDTH/8) - 1 downto 0)
in
s00_axi_wvalid
std_logic
in
s00_axi_wready
std_logic
out
s00_axi_bresp
std_logic_vector(1 downto 0)
out
s00_axi_bvalid
std_logic
out
s00_axi_bready
std_logic
in
s00_axi_araddr
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
s00_axi_arprot
std_logic_vector(2 downto 0)
in
s00_axi_arvalid
std_logic
in
s00_axi_arready
std_logic
out
s00_axi_rdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
s00_axi_rresp
std_logic_vector(1 downto 0)
out
s00_axi_rvalid
std_logic
out
s00_axi_rready
std_logic
in
m00_axi_aclk
std_logic
in
ports of axi master bus interface m00_axi
m00_axi_aresetn
std_logic
in
m00_axi_awid
std_logic_vector(AXI_ID_WIDTH - 1 downto 0)
out
m00_axi_awaddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
out
m00_axi_awlen
std_logic_vector(7 downto 0)
out
m00_axi_awsize
std_logic_vector(2 downto 0)
out
m00_axi_awburst
std_logic_vector(1 downto 0)
out
m00_axi_awlock
std_logic
out
m00_axi_awcache
std_logic_vector(3 downto 0)
out
m00_axi_awprot
std_logic_vector(2 downto 0)
out
m00_axi_awqos
std_logic_vector(3 downto 0)
out
m00_axi_awuser
std_logic_vector(AXI_AWUSER_WIDTH - 1 downto 0)
out
m00_axi_awvalid
std_logic
out
m00_axi_awready
std_logic
in
m00_axi_wdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
m00_axi_wstrb
std_logic_vector(AXI_DATA_WIDTH/8 - 1 downto 0)
out
m00_axi_wlast
std_logic
out
m00_axi_wuser
std_logic_vector(AXI_WUSER_WIDTH - 1 downto 0)
out
m00_axi_wvalid
std_logic
out
m00_axi_wready
std_logic
in
m00_axi_bid
std_logic_vector(AXI_ID_WIDTH - 1 downto 0)
in
m00_axi_bresp
std_logic_vector(1 downto 0)
in
m00_axi_buser
std_logic_vector(AXI_BUSER_WIDTH - 1 downto 0)
in
m00_axi_bvalid
std_logic
in
m00_axi_bready
std_logic
out
m00_axi_arid
std_logic_vector(AXI_ID_WIDTH - 1 downto 0)
out
m00_axi_araddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
out
m00_axi_arlen
std_logic_vector(7 downto 0)
out
m00_axi_arsize
std_logic_vector(2 downto 0)
out
m00_axi_arburst
std_logic_vector(1 downto 0)
out
m00_axi_arlock
std_logic
out
m00_axi_arcache
std_logic_vector(3 downto 0)
out
m00_axi_arprot
std_logic_vector(2 downto 0)
out
m00_axi_arqos
std_logic_vector(3 downto 0)
out
m00_axi_aruser
std_logic_vector(AXI_ARUSER_WIDTH - 1 downto 0)
out
m00_axi_arvalid
std_logic
out
m00_axi_arready
std_logic
in
m00_axi_rid
std_logic_vector(AXI_ID_WIDTH - 1 downto 0)
in
m00_axi_rdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
m00_axi_rresp
std_logic_vector(1 downto 0)
in
m00_axi_rlast
std_logic
in
m00_axi_ruser
std_logic_vector(AXI_RUSER_WIDTH - 1 downto 0)
in
m00_axi_rvalid
std_logic
in
m00_axi_rready
std_logic
out
- ENTITY AXI_MASTER IS
AXI Master component from Vivado that converts the AXI transaction into a simpler memory interface The interface is from the ASTERICS project and further explained in the ASTERIX Documentation.
Generics
PortsGeneric
Type
Default
Description
Port
Type
Mode
Description
- ENTITY MASTER_CONTROLLER IS
The module prioritizes simultaneous memory transaction requests from different cores The core with the lowest index has the highest priority Within a core write requests are prioritized over read requests
Generics
PortsGeneric
Type
Default
Description
AXI_DATA_WIDTH
integer
32
AXI_ADDR_BW
integer
32
NUMBER_OF_CORES
integer
1
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
c_rd_req
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
in
Read request signal from each core
c_wr_req
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
in
Write request signal from each core
raddr
std_logic_vector(NUMBER_OF_CORES * AXI_ADDR_BW - 1 downto 0)
in
Read address from each core
waddr
std_logic_vector(NUMBER_OF_CORES * AXI_ADDR_BW - 1 downto 0)
in
Write address frome each core
out_data
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Data output from core to memory
in_data
std_logic_vector(NUMBER_OF_CORES * AXI_DATA_WIDTH - 1 downto 0)
in
Data input from memory to core
c_wxfer_length
std_logic_vector(NUMBER_OF_CORES * 12 - 1 downto 0)
in
Transfer length for write operations for each core
c_rxfer_length
std_logic_vector(NUMBER_OF_CORES * 12 - 1 downto 0)
in
Transfer length for read operations for each core
c_next_wdata
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
out
If high the specific core should provide the next word
c_next_rdata
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
out
If high the memory provides the next word for the specific core
c_done
std_logic
out
Transaction done
mem_go
std_logic
out
Start the memory transaction (read/write)
mem_clr_go
std_logic
in
Clear the go signal (reset after transaction)
mem_busy
std_logic
in
Indicates memory interface is busy
mem_done
std_logic
in
Indicates successful completion of transaction
mem_error
std_logic
in
Indicates an error occurred during the transaction
mem_timeout
std_logic
in
Indicates the transaction timed out
mem_rd_req
std_logic
out
Request to read from memory
mem_wr_req
std_logic
out
Request to write to memory
mem_bus_lock
std_logic
out
Locks the memory bus during critical transactions
mem_burst
std_logic
out
Indicates a burst memory transaction
mem_addr
std_logic_vector(31 downto 0)
out
Memory address for the transaction
mem_be
std_logic_vector(15 downto 0)
out
Byte enables for selective data access
mem_xfer_length
std_logic_vector(11 downto 0)
out
Length of the memory transfer
mem_in_en
std_logic
in
Enables data input (reading from memory)
mem_in_data
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data read from memory
mem_out_en
std_logic
in
Enables data output (writing to memory)
mem_out_data
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Data to be written to memory
- ENTITY AXI_SLAVE IS
The AXI SLAVE is a vivado generated file that provides register where the host-cpu can read from and write to via the AXI-LITE protocol In its current config there are 8 register. control_command_reg_0 : host-cpu can write and read, hardware can read only control_status_reg_1 : host-cpu can read only, hardware can write only head_reg_2 : host-cpu can write and read, hardware can read only payload_reg_3 : host-cpu can write and read, hardware can read only payload_reg_4 : host-cpu can write and read, hardware can read only payload_reg_5 : host-cpu can write and read, hardware can read only payload_reg_6 : host-cpu can write and read, hardware can read only payload_reg_7 : host-cpu can write and read, hardware can read only
Generics
PortsGeneric
Type
Default
Description
AXI_DATA_WIDTH
integer
32
AXI_ADDR_BW
integer
5
Port
Type
Mode
Description
control_command_reg_0
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Out interface
control_status_reg_1
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
head_reg_2
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
payload_reg_3
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
payload_reg_4
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
payload_reg_5
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
payload_reg_6
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
payload_reg_7
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
clk
std_logic
in
AXI Lite interface
rstn
std_logic
in
s_axi_awaddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s_axi_awprot
std_logic_vector(2 downto 0)
in
s_axi_awvalid
std_logic
in
s_axi_awready
std_logic
out
s_axi_wdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
s_axi_wstrb
std_logic_vector((AXI_DATA_WIDTH/8) - 1 downto 0)
in
s_axi_wvalid
std_logic
in
s_axi_wready
std_logic
out
s_axi_bresp
std_logic_vector(1 downto 0)
out
s_axi_bvalid
std_logic
out
s_axi_bready
std_logic
in
s_axi_araddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s_axi_arprot
std_logic_vector(2 downto 0)
in
s_axi_arvalid
std_logic
in
s_axi_arready
std_logic
out
s_axi_rdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
s_axi_rresp
std_logic_vector(1 downto 0)
out
s_axi_rvalid
std_logic
out
s_axi_rready
std_logic
in
- ENTITY SLAVE_CONTROLLER IS
The module simplifies new_command and command_complete logic for the cores As well as signals the external software which core is ready to receive new commands
Generics
PortsGeneric
Type
Default
Description
AXI_DATA_WIDTH
natural
32
NUMBER_OF_CORES
integer
1
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
c_new_command
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
out
Initiate a new command for each core
c_command_complete
std_logic_vector(NUMBER_OF_CORES - 1 downto 0)
in
Indicates if the command has been completed for each core
head_reg_2_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from head register 2
payload_3_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from payload register 3
payload_4_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from payload register 4
payload_5_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from payload register 5
payload_6_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from payload register 6
payload_7_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output data from payload register 7
control_command_reg_0_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input control command register 0
control_status_1_out
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Output control status register 1
head_reg_2_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to head register 2
payload_3_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to payload register 3
payload_4_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to payload register 4
payload_5_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to payload register 5
payload_6_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to payload register 6
payload_7_in
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Input data to payload register 7
7.3.2. Simulation Setup Modules
- ENTITY MAIN_SIM IS
THANNA_IP_CORE top module for simulation. It contains the engine core top modules and the simulated external DDR memory. The register from the SLAVE CONTROLLER are forwarded to the MAIN_SIM ports. This way, a testbench can instantiate the MAIN SIM top module and send commands to the engine cores like a host-processor would do it. Furthermore the DDR text transaction command signals are forwarded so that the testbench can initialize the memory from a text file and write the results back to the text file.
Generics
PortsGeneric
Type
Default
Description
NUMBER_OF_CORES
natural
2
MEM_SIZE
natural
10000
AXI_DATA_WIDTH
natural
32
parameters of axi slave bus interface s00_axi
AXI_ADDR_BW
natural
32
BASE_ADDR
std_logic_vector
x”40000000”
parameters of axi master bus interface m00_axi
DDR_BASE_ADDR
std_logic_vector
x”00000000”
BURST_LEN
natural
16
ID_WIDTH
natural
1
AWUSER_WIDTH
natural
1
ARUSER_WIDTH
natural
1
WUSER_WIDTH
natural
1
RUSER_WIDTH
natural
1
BUSER_WIDTH
natural
1
Port
Type
Mode
Description
rstn
std_logic
in
clk
std_logic
in
c_set_from_txt_file
std_logic
in
DDR_SIM interface
c_write_to_txt_file
std_logic
in
c_txt_set_txn_done
std_logic
out
c_txt_write_txn_done
std_logic
out
s_axi_awaddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
AXI Slave interface
s_axi_awprot
std_logic_vector(2 downto 0)
in
s_axi_awvalid
std_logic
in
s_axi_awready
std_logic
out
s_axi_wdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
s_axi_wstrb
std_logic_vector((AXI_DATA_WIDTH/8) - 1 downto 0)
in
s_axi_wvalid
std_logic
in
s_axi_wready
std_logic
out
s_axi_bresp
std_logic_vector(1 downto 0)
out
s_axi_bvalid
std_logic
out
s_axi_bready
std_logic
in
s_axi_araddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s_axi_arprot
std_logic_vector(2 downto 0)
in
s_axi_arvalid
std_logic
in
s_axi_arready
std_logic
out
s_axi_rdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
s_axi_rresp
std_logic_vector(1 downto 0)
out
s_axi_rvalid
std_logic
out
s_axi_rready
std_logic
in
- ENTITY DDR_SIM IS
- Generics
PortsGeneric
Type
Default
Description
DDR_BASE_ADDR
integer
0
AXI_DATA_WIDTH
integer
32
AXI_ADDR_BW
integer
32
MEM_SIZE
integer
300
Port
Type
Mode
Description
rstn
std_logic
in
clk
std_logic
in
c_set_from_txt_file
std_logic
in
Memory text interface
c_write_to_txt_file
std_logic
in
c_txt_set_txn_done
std_logic
out
c_txt_write_txn_done
std_logic
out
s_awvalid
std_logic
in
AXI address channel
s_awready
std_logic
out
s_arvalid
std_logic
in
s_arready
std_logic
out
s_awlen
std_logic_vector(7 downto 0)
in
s_awsize
std_logic_vector(2 downto 0)
in
s_arlen
std_logic_vector(7 downto 0)
in
s_arsize
std_logic_vector(2 downto 0)
in
s_awaddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s_araddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
in
s_wvalid
std_logic
in
AXI data channel
s_wready
std_logic
out
s_wdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
s_wstrb
std_logic_vector(AXI_DATA_WIDTH / 8 - 1 downto 0)
in
s_wlast
std_logic
in
s_rvalid
std_logic
out
s_rready
std_logic
in
s_rlast
std_logic
out
s_rdata
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
s_rresp
std_logic_vector(1 downto 0)
out
AXI response channel
s_bvalid
std_logic
out
s_bready
std_logic
in
s_bresp
std_logic_vector(1 downto 0)
out
7.4. AXI_TEST Engine Core Modules
- ENTITY AXI_TEST IS
A core dummy module that emulates the communication with the external memory (-> MASTE_CONTROLLER) with the direct register access (-> SLAVE_CONTROLLER)
Generics
PortsGeneric
Type
Default
Description
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
c_new_command
std_logic
in
New command from the slave controller
c_command_complete
std_logic
out
Command finished to the slave controller
head_reg_2
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Command context register from the slave controller
payload_reg_3
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data register from the slave controller
payload_reg_4
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data register from the slave controller
payload_reg_5
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data register from the slave controller
payload_reg_6
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data register from the slave controller
payload_reg_7
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data register from the slave controller
c_rd_req
std_logic
out
Read request signal to master controller
c_wr_req
std_logic
out
Write request signal to master controller
raddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
out
Read address to master controller
waddr
std_logic_vector(AXI_ADDR_BW - 1 downto 0)
out
Write address frome each core
in_data
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
in
Data output from core to memory
out_data
std_logic_vector(AXI_DATA_WIDTH - 1 downto 0)
out
Data input from memory to core
c_wxfer_length
std_logic_vector(11 downto 0)
out
Transfer length for write operations
c_rxfer_length
std_logic_vector(11 downto 0)
out
Transfer length for read operations
c_next_wdata
std_logic
in
If high provide the next word
c_next_rdata
std_logic
in
If high the memory provides the next word
c_done
std_logic
in
Transaction done
- ENTITY BURST_REG IS
Register that stores and increments data The register contains 256 with the AXI Bus width, which is currently 32 Bit. The module provides always a 32 Bit output word at a certain index The index can be set via c_init_index or incremented via c_next_data If the word at the current index is supposed to be overwritten set c_store on high Every cycle c_increment is high all words in the register get incremented Words can only be stored or incremented if both commands are send, only the current word gets stored
Generics
PortsGeneric
Type
Default
Description
Port
Type
Mode
Description
7.4.1. AXI_TEST Simulation Modules
- ENTITY INTERFACE_TB IS
This testbench simulates currently the AXI_TEST engine core. It wrapps the MAIN_SIM module and therefore has access to the simulated DDR and the AXI_SLAVE interface of the THANNA_IP_CORE. To facilitate the communication to the AXI_SLAVE interface it has an read_reg and write_reg procedure. Test stimulus of the AXI_TEST engine core:
Generics1. the simulated DDR is initialized from a textfile that is generated via the python script in /sim/sim.py. The textfile contains 8 32 Bit words that are incremented. 2. a command is send that the AXI_TEST engine core reads the 8 words from the DDR 3. a command is send that the AXI_TEST engine core increments all 8 words 4. a command is send that the AXI_TEST engine core writes the 8 words back to the DDR 5. the DDR writes the incremented words back to the text file
PortsGeneric
Type
Default
Description
NUMBER_OF_CORES
natural
2
MEM_SIZE
natural
64
AXI_DATA_WIDTH
natural
32
parameters of axi slave bus interface s00_axi
AXI_ADDR_BW
natural
32
BASE_ADDR
std_logic_vector
x”40000000”
parameters of axi master bus interface m00_axi
DDR_BASE_ADDR
std_logic_vector
x”00000000”
BURST_LEN
natural
16
ID_WIDTH
natural
1
AWUSER_WIDTH
natural
1
ARUSER_WIDTH
natural
1
WUSER_WIDTH
natural
1
RUSER_WIDTH
natural
1
BUSER_WIDTH
natural
1
Port
Type
Mode
Description
7.5. GENERAL MODULES
- ENTITY COUNTER IS
On last count c_last is high (lc_counter_end = 4): | clock cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | … | |---|—|---|—|---|—|---|—|---|—| | count | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | … | | c_last | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | … |
Note that if functionality like c_last information or the actual count number is not required one can instantiate the ports with open to remove unecessary logic.
Generics
PortsGeneric
Type
Default
Description
COUNT_BW
integer
16
Bitwidth of the count number
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
c_enable
std_logic
in
Count one up
c_last
std_logic
out
Signals when the counter reached the count limit
count
std_logic_vector(COUNT_BW - 1 downto 0)
out
The count number
lc_count_end
std_logic_vector(COUNT_BW - 1 downto 0)
in
The count limit
- ENTITY SINGLEPORT_BRAM IS
Simple Single Port BRAM component This component writes data into the BRAM on “c_write” high at the address “addr”. The component always reads data at the same address “addr” The component is read first. If data is read and written in the same clock cycle the output data is first read from the addr and then the data in the BRAM is overwritten.
Generics
PortsGeneric
Type
Default
Description
WORD_BW
integer
32
Bitwidth of the data words in the BRAM
ADDR_BW
integer
32
Bitwidth of the BRAM address
Port
Type
Mode
Description
clk
std_logic
in
Clock
c_write
std_logic
in
Write data_in into the BRAM
c_read
std_logic
in
addr
std_logic_vector(ADDR_BW - 1 downto 0)
in
Write and read address
data_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Input data
data_out
std_logic_vector(WORD_BW - 1 downto 0)
out
Output data
- ENTITY DUALPORT_BRAM IS
The dual port block RAM is supposed to be utilized in multiple modules and thus needs to be flexible in terms of its functionality. dual port BRAM is used to store data in block RAM modules, where one can write and read simultaneously to and from the RAM.
Example Behaviour: | clock cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | … | |---|—|---|—|---|—|---|—|---|—| | c_read | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | … | | c_write | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | … | | waddr | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | … | | raddr | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | … | | wdata | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | … | | rdata | U | U | 2 | 3 | 4 | 5 | 6 | 7 | … | | RAM | 0 | 1 | 2 | 3 | 4 | 5 | U | U | … |
Note that for instantiation the same address can be used for raddr and waddr but is not mandatory
Generics
PortsGeneric
Type
Default
Description
WORDS
integer
1024
Number of data words that the BRAM can store
WORD_BW
integer
32
Bitwidth of the data word
ADDR_BW
integer
16
Bitwidth of the storage address
MODE
string
“block”
Synthesis mode (“block” = bram, “registers” = register)
Port
Type
Mode
Description
clk
std_logic
in
Clock
c_write
std_logic
in
Write word in the current cycle
c_read
std_logic
in
Read word in the current cycle
waddr
std_logic_vector(ADDR_BW - 1 downto 0)
in
Address of the write word
raddr
std_logic_vector(ADDR_BW - 1 downto 0)
in
Address of the read word
wdata
std_logic_vector(WORD_BW - 1 downto 0)
in
Word to write
rdata
std_logic_vector(WORD_BW - 1 downto 0)
out
Word to read
- ENTITY FIFO IS
The FIFO BUFFER is used to buffer input data in case the data cant be directly passed to next module. At the moment the FIFO is only designed for a specific use case. To make the module more flexible new functionality is required.
Input / Output: * Each time a new word is written into the buffer on c_enable = ‘1’, the write address is incremented and new data is written into the buffer. * Data is always outputted from the buffer as long as the stream is not halted. If a new word is written, or there is data in the buffer the read address counter gets incremented.and new valid output data is available
Note: The FIFO is at the moment intendet to be used to buffer read bursts. Extend the module if functionality if required. Please update all other modules instantiating it too. Note: The signal c_empty and c_full are only indicators of the storage state. There are no safety measures that can prevent you from overloading the buffer if you ignore the signals.
Generics
PortsGeneric
Type
Default
Description
WORDS
integer
16
WORD_BW
integer
32
INDEX_BW
integer
4
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
c_halt_in
std_logic
in
Halts outputting words
c_empty
std_logic
out
On high, ready to receive new input words
c_full
std_logic
out
One clock cycle away till the buffer is full
c_enable
std_logic
in
New valid input word
c_valid
std_logic
out
New valid output word
full_count
std_logic_vector(INDEX_BW - 1 downto 0)
out
Counter keeps track how full the buffer is
data_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Input data
data_out
std_logic_vector(WORD_BW - 1 downto 0)
out
Output data
- ENTITY DSP_MAC IS
The DSP_M module stands for a DSP that multiplies and accumulates. The trigger c_enable starts the equation a_in * c_in + d_in. The result p_out is given on the next cycle 2 cycles
Note: Variation of XILINX DSP example: https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Pre-Adders-in-the-DSP-Block
Generics
PortsGeneric
Type
Default
Description
A_BW
natural
8
C_BW
natural
8
D_BW
natural
16
P_BW
natural
17
Port
Type
Mode
Description
clk
std_logic
in
rstn
std_logic
in
a_in
std_logic_vector(A_BW - 1 downto 0)
in
Input multiplicant a
c_in
std_logic_vector(C_BW - 1 downto 0)
in
Input multiplicant c
d_in
std_logic_vector(D_BW - 1 downto 0)
in
Input multiplicant c
p_out
std_logic_vector(P_BW - 1 downto 0)
out
Output multiplication result
c_enable
std_logic
in
Multiplication trigger
c_halt_in
std_logic
in
Multiplication disruptor
c_valid
std_logic
out
Valid output
- ENTITY RING_BUFFER IS
The module consist of a SINGLEPORT_BRAM and an address COUNTER that shift shift the data through the bram. Once the last address has been reached the counter jumps back to the start which connects both ends to a ring Each time a jump occurs the c_round_complete signal is set high
Generics
PortsGeneric
Type
Default
Description
DATA_BW
integer
8
Bitwidth of the stored data
MAX_ITEMS
integer
100
Maximum number of items to store
RING_ADDR_BW
integer
14
Bitwidth of the address
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
c_enable
std_logic
in
Valid input to process
c_round_complete
std_logic
out
The data was shifted once through the ring
data_in
std_logic_vector(DATA_BW - 1 downto 0)
in
Input data
data_out
std_logic_vector(DATA_BW - 1 downto 0)
out
Output data
lc_ring_end
std_logic_vector(RING_ADDR_BW - 1 downto 0)
in
Number of bram items
7.6. GENERAL SIMULATION MODULES
- ENTITY COUNTER_TB IS
Testbench for the COUNTER module It includes the following test procedures: * test_rstn: Test resetting the counter * test_c_enable: Test counting up * test_count_cycle: Count to the counter limit * test_interrupts: Test irregular count up pattern
Generics
PortsGeneric
Type
Default
Description
COUNT_BW
integer
3
Port
Type
Mode
Description
- ENTITY FIFO_TB IS
Testbench for the COUNTER module It includes the following test procedures: * test_empty_mode: Test pass through data without halts * test_fill_buffer: Fill the buffer by blocking the output through halts * test_empty_buffer: Empty the buffer after it is full
Generics
PortsGeneric
Type
Default
Description
WORDS
integer
4
WORD_BW
integer
32
Port
Type
Mode
Description
- ENTITY RING_BUFFER_TB IS
Tesbench of the RING_BUFFER module The testbench validates if: * the module shifts the items correctly * times the round end signal correctly
The module is tested with incremented data to detect data loss
Generics
PortsGeneric
Type
Default
Description
DATA_BW
integer
32
MAX_ITEMS
integer
10
RING_ADDR_BW
integer
14
Port
Type
Mode
Description
7.7. SINGLE_ENGINE_CORE Modules
- ENTITY BRAM_CACHE IS
The module BRAM cache has two modes:
In the write mode it is possible to store a fixed number of words in the cache. After load config the write address is 0 and gets incremented automatically after each written word.
In the read mode it is possible to a load words. After load config the starting address is 0 and gets incremented automatically after each word.
Generics
PortsGeneric
Type
Default
Description
MAX_WORDS
integer
100000
Number of words to store
WORD_BW
integer
8
Bitwidth of the data words in the BRAM
VEC_WORDS
integer
8
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
c_halt_in
std_logic
in
Halt the module
c_write
std_logic
in
Valid data to write to the BRAM
c_read
std_logic
in
Read data from the BRAM
c_last_item_in
std_logic
in
Write last item
c_last_item_out
std_logic
out
Last item has been written
load_config
std_logic
in
Load command config
lc_mode
std_logic
in
0 sets the Cache in write mode, 1 to read mode
data_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Input data
data_out
std_logic_vector(VEC_WORDS * WORD_BW - 1 downto 0)
out
Output data
- ENTITY MAC_BLOCK IS
The MAC_BLOCK component computes the sum of multiplications between the weights w_in and the inputs x_in. The output is a single digit x_out.
The component consists of two parts. Pipelined MAC DSP rows that run in parallel and then an adder tree. The longer the rows the longer the computation time, but less adder resources. This is because every DSP in the row also performs an addition that must not be computed in the subquent adder tree.
Note: To configure the relation between length of pipelined DSP rows and number of DSP rows in parallel their multiplication need to be equal to the number of multiplication PAIRS. The relation is configurable by the generic DEPTH which determines the number of pipelined DSPs in a row.
Generics
PortsGeneric
Type
Default
Description
PAIRS
integer
9 * 8
Sum pairs
W_BW
integer
8
Bitwidth of the weights
X_BW
integer
8
Bitwidth of the inputs
DEPTH
integer
9
Number of pipelined DSPs : Depth must be divisible through WINDOW_2DSIZE * CHANNELS
X_OUT_BW
integer
21
Output bitwidths
Port
Type
Mode
Description
rstn
std_logic
in
clk
std_logic
in
w_in
std_logic_vector(PAIRS * W_BW - 1 downto 0)
in
Input weight data
x_in
std_logic_vector(PAIRS * X_BW - 1 downto 0)
in
Input data
x_out
std_logic_vector(X_OUT_BW - 1 downto 0)
out
Output result
c_halt_in
std_logic
in
Halt the module
c_halt_out
std_logic
out
Halt the previous modules
c_last_ws_in
std_logic
in
Last windows slide propagation
c_last_ws_out
std_logic
out
Last windows slide propagation
c_last_cb_in
std_logic
in
Last channel batch propagation
c_last_cb_out
std_logic
out
Last channel batch propagation
c_last_nb_in
std_logic
in
Last neuron batch propagation
c_last_nb_out
std_logic
out
Last neuron batch propagation
c_enable
std_logic
in
Valid input data to process
c_valid
std_logic
out
Valid output data
- ENTITY MAC_PIPELINE IS
MAC_PIPELINE is a row of subsequent DSP modules that perform a sum of multiplications. This is a recursive module that instantiates itelf as much as often as the generic DEPTH. The generic also determines the number of DSPS. Each DSP performs a multiplication and adds the result to the sum.
Generics
PortsGeneric
Type
Default
Description
DEPTH
natural
3
Number of subsequent mac operations
W_BW
natural
8
Bitwidth of the multiplicants w
X_BW
natural
8
Bitwidth of the multiplicants x
D_BW
natural
16
Bitwidth of the summands d
X_OUT_BW
natural
21
Bitwidth of the output
LAST_SINGALS
natural
3
Last signals
Port
Type
Mode
Description
rstn
std_logic
in
clk
std_logic
in
c_enable
std_logic
in
Trigger the mac_pipeline with valid input data
c_valid
std_logic
out
Valid output of the last mac dsp
c_halt_in
std_logic
in
Halt the MAC PIPELINE
c_halt_out
std_logic
out
Forward the halt signal
c_last_in
std_logic_vector(LAST_SINGALS - 1 downto 0)
in
Last signals in
c_last_out
std_logic_vector(LAST_SINGALS - 1 downto 0)
out
Last signals out
w_in
std_logic_vector(DEPTH * W_BW - 1 downto 0)
in
Input multiplicants w for w * x + m
x_in
std_logic_vector(DEPTH * X_BW - 1 downto 0)
in
Input multiplicants x for w * x + m
mac_in
std_logic_vector(D_BW - 1 downto 0)
in
Summands m for w * x + m ! In the fin instantiation the signal is ignored
x_out
std_logic_vector(X_OUT_BW - 1 downto 0)
out
Result data
- ENTITY READ_BUFFER IS
The READ BUFFER listens to the controller and starts read requests until the limit of channel batchaes and neuron batches, given by the controller, has been reached. It keeps track of the batch count and increments the read address accordingly. The read data output is passed as long as the module is not halted. A FIFO prevents that a a halt during a read request leads to data loss. The data is buffered and outputed as soon as the halt ends. The module starts new read request only after the buffer is empty again.
Generics
PortsGeneric
Type
Default
Description
BURST_LEN
integer
128
The number of data words in a burst (Needs to be 2^n)
WORD_BW
integer
32
The number of bits that can a data word contain needs to be the size of the AXI bus
ADDR_BW
integer
32
The addr width of the external memory. It is also specified by the device
INDEX_WIDTH
integer
8
Bits the channel batch count and neuron batch count requires
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
load_config
std_logic
in
Load configuration
c_rd_req
std_logic
out
Read request signal to master controller
raddr
std_logic_vector(ADDR_BW - 1 downto 0)
out
Read address to master controller
data_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Data output from core to memory
c_rxfer_length
std_logic_vector(11 downto 0)
out
Transfer length for read operations
c_next_rdata
std_logic
in
If high the memory provides the next word
c_done
std_logic
in
Transaction done
c_read_in
std_logic
in
Controller command to read
c_halt_in
std_logic
in
On halt no output data is passed
c_valid
std_logic
out
On high there is valid output data
c_last_item_out
std_logic
out
Last item of the burst is outputed
c_last_cb_out
std_logic
out
Last read request of a channel batch
c_last_nb_out
std_logic
out
Last neuron channel batch of a neuron batch
data_out
std_logic_vector(WORD_BW - 1 downto 0)
out
Output data
lc_raddr
std_logic_vector(ADDR_BW - 1 downto 0)
in
Load config ddr address to read from
lc_cb_items
std_logic_vector(INDEX_WIDTH - 1 downto 0)
in
Load config number of data words in a channel batch
lc_nb_items
std_logic_vector(INDEX_WIDTH - 1 downto 0)
in
Load config number of channel batches in a neuron batch
- ENTITY REC_ADDER IS
The REC_ADDER modules produces an adder tree. This module is recursive and instantiates itself upon initial instantiation. Every REC_ADDER module computes one layer of additions in the tree.
Generics
PortsGeneric
Type
Default
Description
BW
integer
8
Bitwdith of the input summands
BW_OUT
integer
19
Bitwidth of the output result
ITEMS
integer
8
Number of summands. This generic is used to generate the ADDER_TREE structure
LAST_SIGNALS
integer
3
Number of last signals to propagate along the computations
BW_REF
integer
8
Bitwidth of the paramters before they were multiplied
SUMS
integer
0
Sums that have been computed in pipelined DSP row
Port
Type
Mode
Description
rstn
std_logic
in
clk
std_logic
in
c_enable
std_logic
in
Valid input to process
c_valid
std_logic
out
Valid output
c_halt_in
std_logic
in
Halt the module
c_halt_out
std_logic
out
Halt the predecent module
c_last_in
std_logic_vector(LAST_SIGNALS - 1 downto 0)
in
Last signals to propagate along computation
c_last_out
std_logic_vector(LAST_SIGNALS - 1 downto 0)
in
Propagated last signals
x_in
std_logic_vector(ITEMS * BW - 1 downto 0)
in
Input data
x_out
std_logic_vector(BW_OUT - 1 downto 0)
out
Output data
- ENTITY RELU IS
The component RELU removes all negative values and quantizises the bitwidth to the size of the single engine core inputs
Generics
PortsGeneric
Type
Default
Description
X_IN_BW
natural
8
X_QUANT_BW
natural
4
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
c_enable
std_logic
in
Valid input data to process
c_valid
std_logic
out
Valid output data
c_halt_in
std_logic
in
Halt the module
c_halt_out
std_logic
out
Halt the previous modules
c_last_ws_in
std_logic
in
Last window slide in
c_last_ws_out
std_logic
out
Last window slide out
c_last_nb_in
std_logic
in
Last neuron batch in
c_last_nb_out
std_logic
out
Last neuron batch out
x_in
std_logic_vector(X_IN_BW - 1 downto 0)
in
Input data
x_out
std_logic_vector(X_QUANT_BW - 1 downto 0)
out
Output data
- ENTITY RING_ACCUMULATOR IS
The RING_ACCUMULATOR module * sets the biases for the output neurons * subsequently add an input x_in to a neuron * switch to the next neurona and add x_in * repeat the last two steps until the output neuron has accumulated all inputs (+ biases) In the last round of additions the output neurons are valid and outputted for further processing
Generics
PortsGeneric
Type
Default
Description
MAX_OUTPUT_NEURONS
integer
16
Maximum number of output neurons / Maximum number of convolutional strides
RING_ADDR_BW
integer
32
Bitwidth of the bram address
X_BW
integer
8
Input x bitwidth
B_BW
integer
3
Bias b bitwidth
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
c_halt_in
std_logic
in
Halt module
c_halt_out
std_logic
out
Halt the previous module
c_enable
std_logic
in
Valid input to process
c_valid
std_logic
out
Valid output
c_last_cb_in
std_logic
in
Last channel batch input
c_last_nb_in
std_logic
in
Last neuron batch input
c_last_ws_in
std_logic
in
Last window slide
c_last_nb_out
std_logic
out
Last neuron batch output
c_last_ws_out
std_logic
out
Last window stride ouput
x_in
std_logic_vector(X_BW - 1 downto 0)
in
Input x
b_in
std_logic_vector(B_BW - 1 downto 0)
in
Bias b
x_out
std_logic_vector(X_BW - 1 downto 0)
out
Output x
lc_keep_result
std_logic
in
This configuration keeps the results in the buffer for the next command
lc_out_neurons
std_logic_vector(RING_ADDR_BW - 1 downto 0)
in
Number of window strides / neurons to process
- ENTITY SLIDING_WINDOW_BUFFER IS
The sliding window buffer can prepare fully connected inputs in the lc_window_only mode and or prepares convolutional inputs otherwise. Load config sets the buffer up. It is possible: * to set the window_only mode * to set the stride during convolution to 2 * to set input image in form of lc_bram_end (lc_bram_end = input_image - kernel) * to disable the module when lc_compute is low
Input comes as a data word and output is delivered as a kernel matrix of words The module propagates last signals It also has an own last signal c_last_ws_out which indicates the end of a fully connected input delivery or convolutional input delivery
TODO: Stride functionality is missing
Generics
PortsGeneric
Type
Default
Description
WORD_BW
natural
32
Bitwidth of the data words
WINDOW_DIM
natural
9
Window dimensions
IMAGE_DIM
natural
100
Max dimensions of the input image
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
load_config
std_logic
in
Load config
x_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Input word
window_out
std_logic_vector(WINDOW_DIM * WINDOW_DIM * WORD_BW - 1 downto 0)
out
Output window matrix
lc_bram_end
std_logic_vector(12 downto 0)
in
Number of items in a bram row
lc_stride2
std_logic
in
On high the stride is 2
lc_window_only
std_logic
in
Window only mode for fully connected layer
lc_compute
std_logic
in
Process inputs
c_enable
std_logic
in
Valid input data to process
c_valid
std_logic
out
Valid output data
c_halt_in
std_logic
in
Halt the module
c_halt_out
std_logic
out
Halt the previous module
c_last_nb_in
std_logic
in
Last neuron batch
c_last_nb_out
std_logic
out
Last neuron batch out
c_last_cb_in
std_logic
in
Last channel batch
c_last_cb_out
std_logic
out
Last channel batch oot
c_last_ws_out
std_logic
out
Last window stride of the SLIDING_WINDOW_BUFFER
- ENTITY WINDOW IS
The window module is a register based 2D matrix that takes an input column on the right and shifts all columns by one step to the right. The matrix itself is the output
Visualization: i = input
0 0 i 0 0 i 0 0 i ->->->
c_enable -> shift all columns one step right
Generics
PortsGeneric
Type
Default
Description
WORD_BW
integer
32
Bitwidth of a word / matrix cell
WINDOW_DIM
integer
9
Window dimensions
Port
Type
Mode
Description
rstn
std_logic
in
Reset negative
clk
std_logic
in
Clock
c_halt_in
std_logic
in
Halt
c_enable
std_logic
in
Valid input to process / shift right
col_in
std_logic_vector(WINDOW_DIM * WORD_BW - 1 downto 0)
in
Input column
window_out
std_logic_vector(WINDOW_DIM * WINDOW_DIM * WORD_BW - 1 downto 0)
out
Output window matrix
- ENTITY WRITE_BUFFER IS
The WRITE BUFFER listens to the controller and starts write requests until the limit of window slides and neuron batches, given by the previous module has been reached. This module contains two FIFOs. One is for buffering the write output data. A write request is only issued when the buffer is full and it is assured the write data is there to be written. This measure is important to not block other write and requests. The second FIFO is an input buffer that is able to still buffer input data when the write buffer is full to perform a write request
Generics
PortsGeneric
Type
Default
Description
BURST_LEN
integer
4
The number of data words in a burst (Needs to be 2^n)
WORD_BW
integer
32
The number of bits that can a data word contain needs to be the size of the AXI bus
ADDR_BW
integer
32
The addr width of the external memory. It is also specified by the device
INDEX_WIDTH
integer
8
Bits the channel batch count and neuron batch count requires
Port
Type
Mode
Description
clk
std_logic
in
Clock
rstn
std_logic
in
Reset negative
load_config
std_logic
in
Load confi
c_wr_req
std_logic
out
Write request signal to master controller
waddr
std_logic_vector(WORD_BW - 1 downto 0)
out
Write address to master controller
data_out
std_logic_vector(WORD_BW - 1 downto 0)
out
Data output from core to memory
c_wxfer_length
std_logic_vector(11 downto 0)
out
Transfer length for write operations
c_next_wdata
std_logic
in
If high the memory provides the next word
c_done
std_logic
in
Transaction done
c_write_in
std_logic
in
Controller command to write
c_halt_out
std_logic
out
On halt no output data is passed
c_enable
std_logic
in
On high there is valid output data
c_last_ws_in
std_logic
in
Last window slide of a set of neurons
c_last_nb_in
std_logic
in
Last neuron channel batch of a neuron batch
c_write_complete
std_logic
out
All the data has been written to the external memory
data_in
std_logic_vector(WORD_BW - 1 downto 0)
in
Output data
lc_waddr
std_logic_vector(ADDR_BW - 1 downto 0)
in
Load config ddr address to write from
7.8. SINGLE_ENGINE_CORE Simulation Modules
- ENTITY BRAM_CACHE_TB IS
This module tests the BRAM_CACHE it tests the write mode and read mode of the module.
Generics
PortsGeneric
Type
Default
Description
MAX_WORDS
integer
100000
Number of words the BRAM is capable to store
WORD_BW
integer
8
Bitwidth of the data words in the
VEC_WORDS
integer
8
Port
Type
Mode
Description
- ENTITY MAC_BLOCK_TB IS
Testbench of the MAC_BLOCK component
Generics
PortsGeneric
Type
Default
Description
PAIRS
integer
9 * 4
W_BW
integer
8
X_BW
integer
8
DEPTH
integer
9
X_OUT_BW
integer
23
Port
Type
Mode
Description
- ENTITY MAC_PIPELINE_TB IS
This testbench tests the module MAC_PIPELINE Input stimuli are the incremented multiplicants w and x Each iteration should produce a specific result that can be checked against the modules valid outputs.
Generics
PortsGeneric
Type
Default
Description
DEPTH
natural
3
W_BW
natural
8
X_BW
natural
8
D_BW
natural
16
X_OUT_BW
natural
19
LAST_SINGALS
natural
3
Port
Type
Mode
Description
- ENTITY READ_BUFFER_TB IS
The testbench of the READ_BUFFER validates if the data is loaded according to the setup and if it manages to successfully buffer the date when the successor halts the pipeline
Generics
PortsGeneric
Type
Default
Description
BURST_LEN
integer
4
The number of data words in a burst (Needs to be 2^n)
WORD_BW
integer
32
The number of bits that can a data word contain needs to be the size of the AXI bus
ADDR_BW
integer
32
The addr width of the external memory. It is also specified by the device
INDEX_WIDTH
integer
8
Bits the channel batch count and neuron batch count requires
CHANNEL_BATCHES
integer
8
Sets the number of channel batches of the READ_BUFFER
NEURON_BATCHES
integer
4
Sets the number of neuron batches of the READ_BUFFER
Port
Type
Mode
Description
- ENTITY RELU_TB IS
Testbench of the RELU component Here every configuration of the RELU is tested One time with clipped negative values and one time without clipped negative values
Generics
PortsGeneric
Type
Default
Description
X_IN_BW
natural
8
X_QUANT_BW
natural
5
Port
Type
Mode
Description
- ENTITY RING_ACCUMULATOR_TB IS
- Generics
PortsGeneric
Type
Default
Description
MAX_OUTPUT_NEURONS
integer
16
Maximum number of output neurons / Maximum number of convolutional strides
X_BW
integer
8
Input x bitwidth
B_BW
integer
3
Bias b bitwidth
Port
Type
Mode
Description
- ENTITY SLIDING_WINDOW_BUFFER_TB IS
This testbench test the SLIDING_WINDOW_BUFFER module in various configurations
Generics
PortsGeneric
Type
Default
Description
WORD_BW
natural
8
WINDOW_DIM
natural
3
IMAGE_DIM
natural
100
Port
Type
Mode
Description
- ENTITY WINDOW_TB IS
This testbench tests the WINDOW module It checks the output of the module during shift the columns and during halt
Generics
PortsGeneric
Type
Default
Description
WORD_BW
integer
32
WINDOW_DIM
integer
9
Port
Type
Mode
Description
- ENTITY WRITE_BUFFER_TB IS
The testbench of the WRITE_BUFFER validates if the data is loaded according to the setup and if it manages to successfully buffer the data when write transaction is blocked by the MASTER
Generics
PortsGeneric
Type
Default
Description
BURST_LEN
integer
4
The number of data words in a burst (Needs to be 2^n)
WORD_BW
integer
32
The number of bits that can a data word contain needs to be the size of the AXI bus
ADDR_BW
integer
32
The addr width of the external memory. It is also specified by the device
INDEX_WIDTH
integer
8
Bits the channel batch count and neuron batch count requires
Port
Type
Mode
Description