8. Simulation

8.1. End-to-end setup

8.1.1. Hardware

The THANNA_IP_CORE module, equipped with AXI interfaces, is designed for direct integration into a simulation environment. This environment includes a SIM_DDR module, which emulates the external DDR memory typically found in FPGA devices. Additionally, the end-to-end testbench simulates the host CPU.

Currently available end-to-end testbenches: - INTERFACE_TB - SECORE_TB (In development)

These testbenches include two main procedures (read_reg and write_reg) to facilitate AXI4Lite communication with the AXI_SLAVE interface of the THANNA_IP_CORE.

Setup Block Diagram:

Overview of the THANNA simulation setup.

The diagram above shows the simulation environment where THANNA_IP_CORE is integrated. The host CPU and external memory are simulated by an end-to-end testbench and a virtual memory module. A file named mem.txt is used to initialize memory and save data. Red arrows indicate command signals, and black arrows represent data signals.

8.1.2. Software

As explained, the simulated DDR can:

  • Be initialized via the mem.txt file

  • Write data back to the mem.txt file

This approach simplifies memory data generation, allowing Python scripts to handle it more efficiently than VHDL. The generation script is located at hw/sim/sim.py. Each line of mem.txt contains 8 bits of binary data since the external memory is byte-addressed, and each line number corresponds to a DDR address.

Example mem.txt content with incremented 32-bit numbers: .. code-block:: txt

00000000 00000000 00000000 00000001 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000011 …

8.1.3. How to simulate

The following is an example of simulating an end-to-end test, using the interface test.

  1. Generate the simulation project: - Navigate to the hardware directory: cd ./hw - Run: make sim_interface - The output mem.txt file will be available immediately for review at hw/out/sim_interface/sim_interface.sim/sim_1/behav/xsim/mem.txt.

  2. For further signal analysis in Vivado: - Open the project in Vivado: vivado hw/out/sim_interface/sim_interface.xpr - To regenerate the text file, use: python sim/sim_interface.py --path out/sim_interface/sim_interface.sim/sim_1/behav/xsim/mem.txt - Optionally, load a corresponding wave configuration file into the waveform viewer in Vivado. For this test, use wavefile/INTERFACE_TB.wcfg. - Start the simulation and analyze the signals.

8.2. Unit Tests

In addition to end-to-end simulation, each module in the core engine should have a dedicated testbench.